1. Field of the Invention
The present invention relates to a method for forming a metal wire that interconnects circuit components in a semiconductor device. More specifically, the present invention relates to a method for forming a metal wire in a semiconductor device which can provide a flat surface while a metal overfilled in a via or a trench by a damascene process is rapidly stripped by means of spin etching and chemical mechanical polishing (hereinafter, referred to as “CMP”).
2. Discussion of Related Art
Generally, a semiconductor device is a device in which an integrated circuit is formed on a silicon wafer by means of a deposition process, a photolithography process, an etch process and so on. In order to interconnect components constituting the integrated circuit, a wire of a metal material such as copper having a relatively high conductivity, i.e., a metal wire is used. In order to form this metal wire, a single or dual damascene process is used.
The damascene process is a process in which a via and/or a trench formed by selectively etching an interlayer insulating film stacked on a lower metal wire is overfilled with a metal material. The surface of the metal wire formed by the damascene process is polished by means of the CMP process.
For example, in case where the via and/or the trench are/is filled with copper by means of the damascene process, if a deposition thickness of copper is below 1 μm, the CMP process is performed at a polishing rate of 6000˜10000 Å/min using slurry for stripping copper, which is commercialized. However, in order to polish the copper film having a thickness of several μm or more such as an inductor by means of the CMP process using the slurry for stripping copper, a very long polishing time is needed. As a result, a large amount of consumables such as slurry and polishing pads are used.
Furthermore, if the copper wire is formed in a next-generation low-dielectric insulating film by means of a damascene process, there occurs a problem that a thin film is peeled off since the mechanical strength of the low-dielectric insulating film is weak. If the polishing pressure and rotary speed are lowered so as to prevent the peel-off phenomenon of the thin film, the amount of consumables used is increased.
Referring to FIG. 1A, if a copper film 19 is formed in an interlayer insulating film 13 formed on a lower metal wire 11 by means of a damascene process, a step occurs on the surface of the copper film 19 due to a difference in the width between a via and a trench. If a CMP process is performed as shown in FIG. 1B, the surface of the copper film 19 is not polished. Consequently, the uniformity of the copper wire 19a is degraded to lower reliability of the semiconductor device. Unexplained reference numeral 17 indicates a barrier film.
Meanwhile, in order to solve the above problem, there was proposed a hybrid process in which most of a metal is stripped by a chemical wet etch process such as spin etching and some of the metal is stripped by the CMP process. Since the spin etching is based on the wet process as shown in FIG. 2, the etching is equally performed regardless of the step of the copper film 29. Therefore, there occurs a problem that the polishing of a final copper wire 29a indicated by dotted lines is fundamentally impossible. In FIG. 2, reference numeral 21 indicates a lower wire, 23 designates an insulating film and 27 indicates a barrier film.